Technology and Science · updated 2h ago · 2 min read
TSMC and Samsung Commit to ASML High-NA EUV Machines for AI Chip Production
TSMC will deploy High-NA EUV machines starting 2030 Samsung aims adoption by 2030, with 12-inch mask transition by 2033
9 of 11 outlets skipped it: intel already processed over a million wafers using High-NA.
11outlets compared
Same story, two versions
tap a side to read it in full
Génération NT
“Samsung vise une production en volume de puces mémoire DRAM dès 2028”Read the original ↗
CNBC
“Samsung said it would use ASML's machines to produce DRAM, a key type of memory, from 2028.”Read the original ↗
Timing precision affects how strongly each outlet implies Samsung’s urgency and competitive lead.
High-NA EUV commitments
Samsung and TSMC have committed to using ASML’s High-NA EUV lithography machines, with Samsung targeting volume DRAM production by 2028 and TSMC aiming to deploy the technology for high-volume advanced node production starting in 2030.
“The High NA machines can print smaller and more intricate patterns.”
The equipment is positioned as critical for printing smaller, more intricate patterns on silicon wafers, and CNBC describes the High NA machines as able to print “smaller and more intricate patterns.”C
CNBC also says the tool “can cost around $400 million,” while Génération NT adds that each machine costs “près de 400 millions de dollars,” framing the investment as a response to explosive AI demand.
Génération NT further ties the adoption timeline to the need for higher transistor density for AI workloads, stating that “la lithographie High-NA est la seule voie connue” to keep scaling without “exploser la consommation énergétique.”
Quotes and industry framing
ASML President and CEO Christophe Fouquet said the adoption would progress first with current 6-inch masks and then with 12-inch masks, adding, “We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative.”
TSMC Chairman and CEO Dr. C.C. Wei framed the effort as value-chain cooperation, saying, “By bringing together expertise from across the industry's value chain, we hope to keep providing the benefits of cutting-edge technology through continuous innovation that lowers barriers and puts advanced solutions accessible at scale.”
In parallel, CNBC reports that TSMC expects High NA use to rise “driven primarily by the increasingly complex transistor architectures required for AI applications,” while also noting that Samsung said it would adopt the technology in 2030 to “extend the DRAM scaling roadmap.”C
Ars Technica adds that the industry’s embrace of high NA EUV photolithography is linked to production gains, describing the change as one that could boost chip production on the new machines by 40 percent.
12-inch masks and next steps
Beyond the High-NA tool commitments, the companies joined an industry initiative to move photomasks from 6-inch to 12-inch, with Quartz saying the initiative targets establishing a 12-inch mask pilot line by 2031 and full production readiness expected by 2033.
“full production readiness expected by 2033”
CNBC describes photomasks as “effectively the stencils used to print the patterns on the wafers,” and says ASML expects benefits including better productivity and lower chipmaking costs from the larger format.C
Génération NT links the mask transition to economics, stating that “Sans cette évolution, les gains de performance seraient en partie annulés par une production moins efficiente,” while also describing the shift as a move from 6 pouces à 12 pouces.
Ars Technica situates the stakes in AI hardware and consumer devices, saying the technology would allow chip designers to implement even smaller features in next-generation chips produced for “AI data centers and consumer electronics such as smartphones, tablets, and laptops.”